The invention is in the field of semiconductor devices in general and integrated circuit semiconductor devices in particular. In one aspect it relates to improved temperature stability for such devices.
One type of IC, the read-only memory (ROM), comprises a matrix array of storage devices, each device permanently encoded to store either a digital "1" or "0". Read-only memories comprised of MOS integrated circuits are well known and consist of an MOS device at each matrix cross point location. Each MOS device can be made to be conductive or nonconductive, in response to coincident applied voltages, depending upon whether one wishes to define a digital "1" or "0". To code a digital "1", for a conductive device, the device is most commonly made with a thin oxide overlying the channel region. To code a digital "0", for a nonconductive device, the oxide is maintained thick over the underlying channel region, thereby in effect providing the device with a high threshold voltage characteristic so that the device remains nonconductive.
MOS devices include a gate, positioned on top of an insulating layer, which gate may be formed of a metal (usually aluminum) or conductive silicon. Although N-channel MOS silicon gate devices are preferred in many applications, in ROM applications, for example, N-channel aluminum gate devices are more desirable. When N-channel silicon gate devices are used for ROM applications, ohmic contact must be made with each individual MOS device in the ROM. This fact necessitates a considerably greater number of pre-ohmic openings, when compared to metal gate ROMs, to provide contact to each device and this consequently expands the area requirements for each MOS device on the ROM integrated circuit. Aluminum gate devices, on the other hand, need only be contacted once per column on the chip and consequently require a smaller area per device, or alternatively permit a greater number of devices on an equal size chip, when compared to a silicon gate device.
A major drawback, however, in the use of aluminum gate devices for ROM application is that aluminum gate devices generally, are not as suitable during temperature bias stress aging as are silicon gate devices. Temperature stability testing of large area integrated circuit capacitors, i.e., essentially the gate portion of an MOS device without associated source and drain regions using aluminum electrodes, indicates that under a positive voltage bias at 200.degree. C., a voltage shift of one or more volts can be expected. Where integrated circuit capacitors are made with conductive polysilicon instead of aluminum, testing under the same conditions reveals a maximum voltage shift of 0.2 volts. It is believed that the aluminum electrode injects electrons (and thus stores charge) into a "dead area", i.e., the oxide layer. A theoretical model derived from capacitance-voltage measurements is disclosed, for example, in White et al., A Study Relating MOS Processes to a Model of the Al-SiO.sub.2 -Si System, National Bureau of Standards Special Publications No. 337, dated 1970. A capacitance-voltage (CV) curve is generated, by applying a voltage ramp to an MOS capacitor, and measuring capacitance versus voltage. If time, temperature, stress, etc., are held constant, the CV curve can be, for a specific device, exactly reproduced. If some condition, e.g., temperature, changes the curve, the MOS capacitor is generally considered unstable and consequently undesirable for the present application.
Based on believing that an aluminum electrode is an injecting contact whereas a polysilicon electrode is not (or is, at least, less effective as such) it has been proposed to use a thin layer portion of polysilicon in the gate area of an N-channel aluminum gate MOS device, i.e., underneath the aluminum gate layer portion. There is, however, one further constraint in using such a composite metal gate structure: it is desirable not to introduce additional photolithographic steps which would increase processing cost and complexity and would further require tight registration between the polysilicon and metal masks. Moreover, it would be desirable to maintain the high performance of standard metal gate processes, i.e., high gain and low body effect.
The use of a structure of polysilicon and aluminum layers is discussed in Bellier et al., An Improved Process for Silicon Transistors, Extended Abstracts, Volume 73-1, Abstract 125, 1973 and Duncan, U.S. Pat. No. 3,740,835, but for entirely different reasons than the subject invention. In Bellier et al., polysilicon is deposited prior to aluminum deposition in a bipolar transistor in the ohmic regions for the purpose of eliminating silicon dissolution pits under metal contacts. In Duncan, a layer of polysilicon is deposited, at least in the ohmic areas and preferably over the oxide surface of a bipolar transistor, followed by a layer of aluminum to allow good ohmic contact to shallow semiconductor regions. Thus, the layered structure of polysilicon and aluminum which have been mentioned in the literature have been for a different purpose and in a different setting from this invention, which is directed to a particular type of composite structure of polysilicon and aluminum in the gate area of an MOS device, for a purpose different from this prior art, and teaches removal of the polysilicon from the ohmic regions. A process disclosed in Paivinen et al., U.S. Pat. No. 4,011,105, for example, may be modified to achieve the desirable ends of this invention.